Home - Hardware - Viewfinder - Technical details
The Viewfinder hardware itself is not very complex (see below for schematics). It consists of a standard expansion card plug on one 'side' (interfacing with the host machine), a standard AGP video card socket on the other 'side' (interfacing with the AGP video card), and a CPLD 'in between' the two. Plus a few quite ordinary extra bits.
The 'intelligence' is inside the CPLD (Complex Programmable Logic Device), in this case a 144-pin Altera MAX 3000 series chip, the EPM3256ATC144-10, operating at 3.3 V with 5 V tolerant inputs, containing 5000 logic gates (256 macro cells). It neatly interfaces the 5 V based world of the Risc PC with the 3.3 V based AGP interface. Inside it is a custom hardware design of a complexity roughly equivalent to a combination of something like a hundred ordinary logic chips. Almost all of the CPLD's macro cells are needed to perform the functions required by Viewfinder. Most are consumed by the AGP cycle state machine (translating Risc PC bus reads/writes to AGP bus reads/writes) and the logic performing the 'byte swaps' needed to translate the Risc PC's 'aBGR' memory arrangement to the AGP card's 'aRGB' one.
The hardware development was quite complicated and challenging on its own. But, to coin a phrase, well and truly a walk in the park compared to the software development.
To illustrate, the current version of the software, 1.63, consists of around 900 KB of pure (ARM) assembler source code, producing around 95 KB of machine code. Remember we're on quite a different platform than an x86 box running Windows. We're on an ARM platform running RISC OS. There's no using the standard Windows drivers, or even the BIOS. All that has become worthless. Every single piece of software had to be built from the ground up, using rough documentation (mostly consisting of very long lists of rather superficial register descriptions) and hardly any, and certainly no useful, example code to speak of.
A whole lot of time was spent on developing the initialisation routines for all the supported AGP cards, around 15 in total, using either an ATI Rage Pro, Rage 128 or Radeon chipset, but all with slight differences in, for example, memory configuration. Relevant information had to be gathered by painful and strategic disassembly of all the different BIOSses, some plain trial and error guesswork, and a few small hints from XFree86 source code. Only when Radeon was to be supported, and being tired of tweaking the code yet again to support yet another AGP card, I decided to write an 80386 processor emulator, to be able to run the initialisation routines in the AGP card's BIOS directly. Although writing the emulator was hardly 'ten minutes work' (it weighs in at around 100 KB of carefully crafted assembler source code), it was worth it in the end. Once the BIOS has initialised the AGP card, differences with other AGP cards using the same chipset have mostly disappeared.
Just about an equal amount of time was spent on developing all the other, more 'useful' aspects (from an end user point of view) of the software, like screen mode programming, acceleration functions, RISC OS trickery, special features like dual-head, and so on.