Home - Hardware - GoMMC - Technical details
The GoMMC hardware itself is not very complex (see below for schematics). It consists of a BBC ROM socket connector, a memory chip, a CPLD, an MMC socket, and a few quite ordinary extra bits.
The 'intelligence' is inside the CPLD (Complex Programmable Logic Device), in this case a 44-pin Altera MAX 3000 series chip, the EPM3064ALC44-10, operating at 3.3 V with 5 V tolerant inputs, containing 1250 logic gates (64 macro cells). It neatly interfaces the 5 V based world of the BBC with the 3.3 V based MMC interface. Inside it is a custom hardware design of a complexity roughly equivalent to a combination of several tens of ordinary logic chips. Almost all of the CPLD's macro cells are needed to perform the functions required by GoMMC. Most are consumed by the logic performing (8-bit) serial to parallel and parallel to serial conversion (because MMCs have a serial interface).
The memory chip is a special case as well. It is a 32 K byte Ramtron FRAM chip, which is basically an ordinary static RAM chip, but is non-volatile as well (i.e. it remembers its contents after power is removed). GoMMC's sideways ROM software (which has to be present on power-up), and the RAM workspace it requires, could therefore be combined (which means no claim on the BBC's main RAM is necessary, improving GoMMC's 'neutrality').
The hardware design was reasonably straightforward, and did not require any complex logic. Software development, as always with this type of project, was considerably more time consuming.
The software currently consists of around 250K of pure (6502) assembler source code, some BASIC utility code, and around 70K of C++ code. Around half of this is 'core' code (the GoMMC sideways ROM and filing system patches), the other half is utilities. Quite a lot of time was spent disassembling the (now eleven) supported filing systems, in order to patch them for use by GoMMC, but by far most time was spent (between them probably evenly so) on the GoMMC sideways ROM and the utilities.