Home - Hardware - GoMMC - Technical details
The GoMMC hardware, in overview, is not very complex (see below for schematics). It's basically a BBC ROM socket connector, a memory chip, an MMC socket, a CPLD to connect them all, and a few quite ordinary extra bits.
The bulk of the hardware design is actually inside the CPLD (Complex Programmable Logic Device). In this case a 44 pin, 64 macro cell Altera MAX 3000 series chip. It neatly interfaces the 5 V world of the BBC with the 3.3 V world of the MMC. Inside the CPLD is an intricate custom hardware design of a complexity roughly equivalent to fifteen ordinary logic chips. Almost all macro cells are used. Most are consumed by the logic performing serial to parallel and parallel to serial conversion (because MMCs have a serial interface).
The memory chip is a special case as well. It is a 32 KB Ramtron FRAM chip, which is basically an ordinary static RAM chip, but is non-volatile as well (i.e. it remembers its contents even when power is removed). It neatly combines three tasks : holding the GoMMC ROM software, providing its workspace, and serving as non-volatile configuration memory.
The hardware design was reasonably straightforward, and did not require any complex logic. Software development, as always with this type of project, was considerably more time consuming.
The current version of the software weighs in at around 250 KB of pure 6502 assembly source code, 90 KB of C++ source code, and some BASIC utility code. Around half of this is 'core' code (the GoMMC sideways ROM and filing system patches), the other half is utilities. Quite a lot of time was spent disassembling the 11 supported filing systems, in order to patch them for GoMMC, but by far most time was spent (between them probably evenly so) on the GoMMC sideways ROM and the utilities.